Several prior art methods exist for manufacturing semiconductor devices in packages. FIG. 10 is a flow chart illustrating the prior art of manufacturing multi-chip modules using a deposition method (MCM-D). In this method, layers of a substrate are built sequentially one on top of another. After each layer is built, each layer is tested. In a manner well known in the art, a power substrate is first built (step 1001). After manufacture, the power substrate is tested (step 1002). The next layer, a thin film substrate 1 (TFS1), is deposited on the top surface of the power substrate in a manner well known in the art (step 1003). The partially assembled substrate is tested (step 1004). If the partially assembled substrate fails the test, it must be either reworked or discarded. In the latter alternative, a good power substrate is discarded as part of the failed partially assembled substrate. A second thin film substrate (TFS2) is deposited on the first thin film substrate (TFS1) (step 1005) and tested (step 1006). As with the first thin film substrate, the entire partially assembled substrate must be reworked or discarded if it fails the test at step 1006. This process is continued until the Nth layer of the thin film substrate (TFSN) is deposited on the sequentially assembled substrate (step 1007) and tested (step 1008). Parallel to the assembly of the substrate, the chip is assembled (step 1009) and tested (step 1011). After the substrate is assembled and successfully tested, the successfully tested chip is attached to the substrate using a chip attachment technique which is well known in the art (step 1012).
This MCM-D assembly process allows high density interconnections because the deposition process uses standard photolithography techniques which provide small signal traces, small intertrace distances, and close alignment between successive substrate layers. However, this method has several drawbacks. First, a layer requiring a higher annealing temperature must be manufactured before layers requiring lower annealing temperatures thereby imposing potentially severe limitations upon the design and packaging of the semiconductor devices. For example, a thin film capacitor layer made from tantalum pentoxide (Ta.sub.2 O.sub.5) is annealed at temperatures between 600.degree. and 800.degree. centigrade for approximately one minute. The other substrate layers are typically made of other dielectrics which typically have lower stability temperatures. For example, one typical material is polyimide which is stable up to 400.degree. centigrade. Thus, the thin film capacitor layer must be made before the polyimide layers and consequently the capacitor layer can not be the top layer. For some electrical circuits, it is desirable that the capacitor layer be as close to the chip as possible. In this instance, the physical limitations of the substrate limit the electrical performance of the corresponding circuit.
Second, sequentially building the layers using an MCM-D method also provides low overall yields. For example, if one layer has a manufacturing yield of 90% and a second layer has a manufacturing yield of 90% the average overall yield of manufacturing the two layers is 81%. As the number of layers increases, the overall yield correspondingly decreases. In some designs, one module layer may have a yield on the order of 50%. If this layer is built at a later stage, a large number of good partially assembled layers are discarded after the low yield layer is added. Thus, to reduce the manufacturing costs, low yield layers are typically designed to be one of the first manufactured layers. This places additional constraints on the electrical design of the semiconductor device and package.
FIG. 11 is a flow chart illustrating the prior art of fabricating a multi-chip module using a laminated method (MCM-L). Unlike the MCM-D method, the MCM-L method manufactures layers in parallel. The first through the Nth thin film substrates (TSFI . . . TSFN) are manufactured in parallel (steps 1101, 1102, 1103). In addition, the power substrate is also manufactured in parallel (step 1104). Each substrate layer is subsequently individually tested (steps 1106, 1107, 1108, 1109). After successfully passing testing, the substrate layer is stripped from the thin film substrates to form a thin layer of deposited material containing interconnection traces and vias (steps 1111, 1112, 1113). The thin layers are then combined with the power substrate to form the substrate layer (step 1114). This combination requires that an interconnection contact on one substrate layer to be electrically connected to a corresponding bond pad on another substrate layer. To laminate the layers together, the layers are lined up so that the bond pads are opposite each other in spaced apart relation. A bonding material such as epoxy is placed between the substrate layers and cured to provide a rigid mechanical structure. To connect the spaced apart bond pads, the rigid structure is drilled to form a bore that extends through the electrical conductors that are to be connected from one surface of the rigid structure to another surface on the opposite side of the rigid structure (step 1116). The bores are then metallized by plating or other processes known in the art to thereby provide an electrical path between the bond pads on separate substrate layers (step 1117). In a manner similar to that described above in FIG. 10, the chips are assembled (step 1118) and tested (step 1119). Chips passing electrical test are then coupled to the carrier (step 1120).
The MCM-L method has many drawbacks. First, the stripped thin film substrate layers are thin and flexible so that when the substrate layers are handled while placing them in spaced apart relation, the layers tend to warp. The warping causes corresponding bond pads to become misaligned. Second, the process of placing bonding material between substrate layers limits the minimum thickness of the assembled substrate. Third, the rigid mechanical structure is mechanically drilled. Mechanical drill bits have a smallest diameter of about 150 microns. This limits the pitch between the electrical conductors in the substrate.
If a semiconductor device can be divided into separate layers that are capable of being manufactured and tested individually, drawbacks including those identified above are circumvented. For example, two layers requiring different annealing temperatures can be manufactured individually and then combined into a final product. Moreover, as devices are formed by combining only those layers which have already been tested, overall yield will be limited only by the yield of the assembling step, and should thus even be higher than 90%.
Furthermore, as individual layers are manufactured and tested in parallel, manufacturing time of a device is shortened.